New technologies often take a long time to come into common use, if they ever do. Sometimes the time has to be right, the need great enough. With the increasing use of IoT technology, the rise of AI applications at the edge and endpoints and the rise of new communications networks, low power has become an important requirement in modern technology. In addition, pressure to lower the power usage of data centers to meet green data center specifications are causing even the largest computer systems to look at ways to decrease power.
Volatile memories such as DRAM and SRAM are critical to modern computers, servers and consumer electronics. But these memory technologies require data refreshes and power to maintain their data. The refreshes needed for DRAM consume power and SRAM loses its data when power is turned off. Nonvolatile memory technologies don’t require refreshing and allow going into low power states when the device isn’t needed. For nonvolatile memory technologies, the time is right, the need is great.
MRAM (magnetic random access memory) is one of the non-volatile memory technologies that has been under development for decades, and Everspin has shipped over 100 M units of standalone MRAM chips for numerous cache and buffering applications. Most major foundries are now offering MRAM options for embedded and computing applications. At the 2019 IEEE IEDM conference (organized by the IEEE Electron Devices Society, EDS) and at the companion IEEE MRAM Global Innovation Forum (organized by the IEEE Magnetics Society) there were many presentations and posters showing the current progress and future of MRAM.
Bernard Dieny and Tom Coughlin at the 2019 IEEE IEDM
Photo from Tom Coughlin
At the 2019 International Electron Devices Meeting (IEDM) and MRAM Global Innovation Forum I met with Bernard Dieny, Chief Scientist from Spintec in Grenoble France (he is on the left and me on the right, above) and he shared some history of the MRAM technology, that I will share with you. He shared the chart showed below giving a visual history of the technology.
Graphical History of MTJ MRAM
Chart from Bernard Dieny
The R&D on MRAM based on magnetic tunnel junctions (MTJ) started in 1995 with the observation of tunnel magnetoresistance at room temperature independently by Moodera (MIT) and Miyazaki from Tokyo University. Before this discovery MRAM based upon anisotropic magnetoresistance and upon spin-valves were developed by companies such as Non Volatile Electronics, with much lower memory density.
In 1996 John Slonczewski from IBM Research and Luc Berger from CMU independently predicted the phenomenon of Spin Transfer Torque (STT). In 2000 J.A. Katine, et al. made the first observation of switching by STT in metallic pillar at Cornell University. Also, in 2000 W.H. Butler et al., from Oak Ridge National Laboratory predicted giant tunnel magnetoresistance in crystalline MgO tunnel junctions.
In 2002 S.B. Monso et al. from Spintec, discovered interfacial perpendicular magnetic anisotropy (PMA) at magnetic metal/oxide interfaces. In 2004 S.S.P. Parkin et al., from IBM Almaden, as well as S. Yuasa et al., from AIST in Ibaraki , Japan, observed giant tunnel magnetoresistance through MgO based magnetic tunnel junctions (MTJs). Also, in 2004 Y. Huai et al. from Grandis and G.D. Fuchs et al. from Cornell University observed STT switching in MTJs.
In 2006 the first commercial MRAM chips were launched by Everspin using field written toggle MRAM. In 2010 S. Ikeda, et al., from Tohoku University demonstrated a fully out-of-plane magnetized magnetic tunnel junction based upon interfacial PMA and switchable by STT. In 2011 and 2012 I. Miron et al., from Spintec and L. Liu from Cornell University discovered spin orbit torque switching. In 2013 Everspin launched the first 64bit STT-MRAM products.
Finally in 2018 major foundries and integrated device manufacturers announced that they would offer eMRAM options for embedded SoCs and other chips. These included Global Foundries, Intel, Samsung and TSMC). The eMRAM is used to replace embedded NOR as well as higher level cache SRAM and even some DRAM applications. While STT-MRAM is shipping now with capacities up to 1 Gb and increasing in the near future, eventually even faster spin orbit torque (SOT) MRAM could achieve performance of the fastest SRAM technology, making the entire memory hierarchy non-volatile.
The future of memory is non-volatile as emerging memories such as MRAM begin to replace traditional volatile SRAM and DRAM, enabling new IoT and AI applications.