Although today’s news of AMD’s proposed acquisition of Xilinx is likely going to garner the lion’s share of media attention in the short term, the adaptive computing leader concurrently announced a new line of silicon solutions that could significantly impact 5G network build-outs in the future.
Earlier today, Xilinx revealed a its Zynq RFSoC DFE (Digital Front-End), which represents a news class of adaptive radio platform that combines hardened DFE blocks with adaptable logic in an effort to provide flexible solutions for the quickly advancing 5G ecosystem. The Zynq RFSoC DFE is designed for high-performance, cost and power-efficient 5G NR (New Radio) applications covering 5G low-, mid-, and high- band spectrum where Xilinx Zynq UltraScale+ MPSoC and RFSoC products have previously been deployed.
“For the first time, Xilinx is providing a wireless radio platform with more hardened application-specific IP than adaptive logic to address low power and low cost 5G requirements,” said Liam Madden, executive vice president and general manager, Wired and Wireless Group at Xilinx. “With the market needs around 5G evolving, integrated RF solutions need to be adaptable to address future standards. Zynq RFSoC DFE provides the optimal balance between that adaptability and fixed function IP.”
Xilinx is well known for its various, adaptable FPGA technologies. The Zynq RFSoC DFE marries some of that programmable gate array tech, with hard logic to address known quantities, while also providing the flexibility to adapt to the changing 5G market needs of tomorrow. The Zynq RFSoC DFE incorporates established DFE functions in the hardened, ASIC-like silicon, which are configurable for both legacy 4G and 5G NR standards. It marries that hardened IP with a programmable and adaptive SoC to offer increased flexibility, scalability, and intrinsic time-to-market benefits.
The solution Xilinx puts forth with the Zynq RFSoC DFE reportedly provides double the compute resources per antenna versus previous-gen products, but with competitive cost and power characteristics. Conversely, the Zynq RFSoC DFE can also offer significant power reduction for similar use cases compared the previous-gen products, when the DFE hard IP blocks are being fully utilized.
The hardened IP cells in the Zynq RFSoC DFE require less silicon real estate and can reduce power consumption by up to 80% versus traditional FPGAs. A side effect of the hard IP cores’ smaller physical dimensions is that Xilinx can pack more cores onto the device and maximize DFE compute resources compared to its previous-gen and competitive solutions.
The Zynq RFSoC DFE features up to 16 RF-ADCs and 16 RF-DACs, eliminating the need for a JESD204 multigigabit serial interface between converters and a receiver interface. That results in significant power reductions, while also decreasing board area and minimizing the complexity of a total radio solution. According to Xilinx, the power savings is most pronounced when using 64T64R massive MIMO radios, where total power can be reduced by up to 60 watts.
“As 5G continues to evolve in both commercial deployments and new use cases, it is critical for the supply chain to provide flexible components for vendors to create cost effective, adaptive and future-proof equipment. Open RAN takes this requirement to a much higher level, where flexible designs are paramount to its success,” said Dimitris Mavrakis, senior research director of 5G at ABI Research. “With its balance of hardening and adaptable logic, Zynq RFSoC DFE is a unique offering which combines the cost characteristics typically found in ASICs while providing the design flexibility and customization available in an FPGA.”
The continually evolving 5G standards and diversity of potential use cases will likely require multiple ASICs to fully address 5G market requirements. Development costs for ASICs on advanced 10nm and 7nm process nodes are relatively high, however, and the historic benefits of lower unit cost and power with ASICs are not always realized in the current climate. The Zynq RFSoC DFE’s adaptability can mitigate evolution costs dramatically, thanks to its blend of hard IP and programmable logic that can be optimized over time for evolving 5G applications.
Xilinx has already made Zynq RFSoC DFE design documentation and support materials available to early access customers, though shipments of hardware are not expected until the first half of 2021. Further, upon the fruition of its agreement to be acquired, Xilinx could obviously help put AMD squarely on the map for significant relevance in the global 5G roll-out.